The present invention generally relates to fabrication of semiconductor devices and more particularly to a fabrication method of a semiconductor device having a very shallow junction.
With recent highly miniaturized, ultra-fast semiconductor devices, having a gate length of typically 90 nm or less, such as the one having the gate length of 50 nm or 40 nm, the diffusion regions constituting the source and drain regions of the transistor have a very shallow depth of about 20 nm or less.
When fabricating such a semiconductor device having a very shallow junction, particular caution has to be taken in the dry etching process that exposes the diffusion region.
With regard to the dry etching process used in the fabrication process of a MOS transistor, there can be two situations in which the dry etching process causes exposure of the diffusion regions, the first being the one used for forming a contact hole in an insulation film, and the other being the one used for forming sidewall insulation films on the sidewall surfaces of the gate electrode. In any of these processes, it is generally practiced to carry out the etching process of the insulation film by using a fluorocarbon (CF) family gas or hydrofluorocarbon (CHF) family gas for the etching gas.
At the time of the dry etching of an insulation film with an etching gas of the CF or CHF family gas, plasma is used for causing dissociation in the etching gas to form radicals or ions of active species such as F (fluorine) contained in the etching gas, and the ions of the active species thus formed are caused to react upon the substrate to be processed by accelerating the same by using a substrate bias electric field. Further, at the time of such an etching process, it is generally practiced to carry out so-called overetching, in view of possible variation of the film thickness or variation of the etching rate, in which the etching is continued for a predetermined duration after the silicon substrate surface is exposed, such that the silicon surface constituting the diffusion region is exposed completely.
On the other hand, with such an overetching process, it is generally unavoidable that the silicon surface is etched more or less as a result of the action of the etching gas to the exposed silicon surface. Particularly, the silicon surface tends to be etched by F.
In view of the situation noted above, there is an increasing tendency to use gases of high C (carbon) proportion such as C4F8 or C4F6, for the CF or CHF family etching gas, for suppressing the etching of the silicon surface and thus increasing the etching selectivity at the time of the overetching process. By using such an etching gas of high C proportion, there is caused deposition of C on the silicon surface exposed by the etching, and the undesirable etching of the silicon surface at the time of the overetching is suppressed.    (Patent Reference 1) Japanese Laid-Open Patent Application 8-78352    (Patent Reference 2) Japanese Laid-Open Patent Application 9-129602    (Non-Patent Reference 1) K. Hashimi et al., Jpn. J. Appl. Phys. vol. 35, (1996), pp. 2494